The present invention relates generally to semiconductor manufacturing and, more particularly, to a method and apparatus for linking reticle manufacturing data.
Manufacturing modern integrated circuit devices requires the performance of many complex processes, such as deposition processes, etching processes, ion implant processes, and photolithography processes. In general, photolithography involves the formation of a patterned layer of photoresist above a previously formed process layer. Ultimately, the underlying process layer will be subjected to one or more etching processes while using the patterned layer of photoresist as a mask. This will result in the selective removal of the portions of the process layer that are not protected by the photoresist masking layer. That is, a plurality of features, e.g., gate electrode structures, metal contacts, etc., will be formed in the underlying process layer. The patterned layer of photoresist is then removed and additional process operations are performed, e.g., additional layers of material are formed and selectively etched, until such time as the integrated circuit device is completed.
Photolithography is one of the most important, expensive and time-consuming processes performed in a modern integrated circuit manufacturing facility. In the photolithography process, a layer of photoresist material (positive or negative) is deposited on a process layer that has been formed above a semiconducting substrate, i.e., a wafer. Thereafter, the layer of photoresist is selectively exposed to a light source. More particularly, during the exposure process, radiant energy, such as ultraviolet light or deep ultraviolet light, is directed through a reticle to selectively expose the layer of photoresist. In this manner, the pattern in the reticle is transferred to the layer of photoresist. The layer of photoresist is then developed to remove the exposed portions of the layer of photoresist (for a positive resist material) to thereby define a patterned photoresist mask that is used in the subsequent etching of the underlying process layer. For negative photoresist materials, the unexposed portions of the layer of photoresist are removed during the development process. Additionally, the layer of photoresist is exposed to the light source on a flash-by-flash basis in a stepper exposure tool. The number of production die in each flash pattern may vary, e.g., a 2×2 pattern (4 die), a 2×4 pattern (8 die), etc. This step-by-step exposure process is continued until all of the areas of the production die on the wafer are exposed.
The manufacture and patterning of a reticle is a very time-consuming and expensive process. A reticle for use in manufacturing a modern integrated circuit product may cost between $25,000-$75,000, depending upon the type of reticle and the complexity of the reticle pattern. A reticle typically includes a transparent substrate comprised of, for example, quartz or glass. A very thin, opaque film is formed above the transparent substrate. The opaque film may be comprised of a variety of materials, such as chromium. To form the pattern in the reticle, a layer of photoresist material, e.g., a positive photoresist material, is formed above the opaque film, and an electron beam is used to expose selected portions of the layer of photoresist. Thereafter, the exposed portions of the layer of positive photoresist are removed, thereby exposing portions of the underlying opaque film, e.g., chromium. An etching process is then performed using the patterned layer of photoresist as a mask to remove the exposed portions of the opaque film, resulting in the desired pattern in the opaque film. The patterned layer of photoresist is then removed, and the reticle is ready for use in the photolithography process as described above.
Typically, a semiconductor manufacturer will provide the desired pattern for the reticle to a vendor that manufactures reticles. The specification documents provided to the vendor specify those features to be manufactured on the reticle that are deemed important by designers. Such features are referred to as target features herein. Generally, the target features represent features that are selected by the device designers for verification. After the manufacture of the reticle, the vendor typically provides a certificate of conformance (CofC) indicating verification tests that were performed to certify that the reticle meets the design requirements with respect to the target features.
Typically, data and requirements associated with the design and fabrication of reticles are not related to the final integrated circuit device. This lack of association between design and production data makes it difficult to evaluate the implementation of the design in the final product, and hence, hampers the ability to implement design changes to improve performance or yield, or to troubleshoot design-induced manufacturing problems.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.